Microprocessors and embedded system design university of electronics, china, end-of-doc chapter an

7.() is still recognized as the basic architecture of most commercial computers at present。

Reference answer:

Von neumann

8. In the software and hardware stratification model of computers, including 1 command system, 2 digital logical circuits, 3 operations

Systems, 4mos tubes, 5 applications, etc., are in descending order ()。

Reference answer:

42135

Mips is usually used to describe the computer's operating speed, meaning ()。

Reference answer:

Millions of instructions per second

10. The following description of the structure of the von noyman system is incorrect (...)。

Reference answer:

The computer consists of five components of cpu, bus, storage, input and output equipment

The similarities between cache and virtual storage technologies do not include ()。

Reference answer:

The main objective is to increase computer speed

12. Software and hardware in computer systems are logically equivalent and increasing the proportion of software functionality achieved will be ()。

Reference answer:

Increased system flexibility

With regard to the flow of command streams in von neumann's computer, the following is correct。

Reference answer:

Storage to controller

14. In the flynn classification of the structure of the computer system, there is currently no actual realization type ()。

Reference answer:

Multiple command order data misd

“64” of 64 computers is usually referred to (it)。

Reference answer:

The maximum number of digits within the cpu for one-time processing is 64

16. The techniques listed below for improving the system performance of microprocessors are not correct ()。

Reference answer:

The implementation time of each instruction has been significantly reduced with the introduction of streaming line structures

17. The following are the characteristics of over-standard microprocessors ()。

Reference answer:

Internal with multiple command flow lines (parts)

According to the flynn classification, the traditional von noyman computer corresponds to the structure。

Reference answer:

Sisd

19. The width of a data bus may be inferred from the 32-bit width of a microprocessor address。

Reference answer:

There's no automatic connection to the address bus

20. Usually we refer to a series of machines with the same () computer。

Reference answer:

Structure

The following components are external to the computer:。

Reference answer:

Web

22. The components of computer hardware not defined in the structure of the von noyman system are (...)。

Reference answer:

Bus

The following are the computer system hardware:。

Reference answer:

Memory bar

24. The currently executed segment of the computer should be kept in ()。

Reference answer:

Memory

The following are not part of the general cpu function(s)。

Reference answer:

Storage command

26. According to the flynn classification of the computer system structure, vector processors (array processors) should generally be

I'm sorry。

Reference answer:

Single command stream multiple data stream simd

The following factors are not considered in the design of the computer system structure:。

Reference answer:

Whether the cpu chip uses the 5 nmcmos process

With regard to the description of risc and cisc, the error is ()。

Reference answer:

The former usually do not use current line structures to reduce complexity

29. When designing the over-standard structure, the flow segment of multiple parallel modules should be ()。

Reference answer:

Maximum period of implementation

With regard to the system address bus for microprocessors, the following statement is correct。

Reference answer:

Address code for different ports in the interface

With regard to control information maintained in i/o interface circuits, the correct statement is ()。

Reference answer:

Data bus from the microprocessor system

32. For a low-speed offset, the microprocessor hopes to do data only when the data is ready. Hand it over

Each other. To complete this data transfer requirement, it is preferable to opt for ()。

Reference answer:

Interrupt transmission

33. With regard to the technology of disruption in the microprocessor system, the following statement is correct。

Reference answer:

It reduces the microprocessor burden

In the microprocessor system, the interruption vector usually refers to ()。

Reference answer:

Entry address for interrupted service

35. In addition to the performance of the i/o equipment itself, the main factors affecting the speed of transmission of data from the embedded system i/o

Yes。

Reference answer:

Transmission rate for bus

36. The following statement on dma is incorrect。

Reference answer:

The data to be transferred through the cpu controller

37. In the microprocessor system, the general interruption type number is ()。

Reference answer:

Number of interrupted service procedures

The primary role of the memory management module mmu in the page-distributed storage system is ()。

Reference answer:

Manage address map

39. The following statement of interruption is correct。

Reference answer:

Allow nesting while interrupting response

The purpose of protection of breakpoints is () when the microprocessor system response is interrupted。

Reference answer:

After completion of the interrupted service program, correct return of the interrupted program

41. An external interface contains two data ports, meaning ()。

Reference answer:

At least two data repositories are required for this interface

42. In multitasking systems, to improve the efficiency of cpus, low-speed outsourcing should take place after data are ready

Cpu was notified of the data exchange. () i/o is best used to complete this data transfer。

Reference answer:

Interrupt

For input output, there is a description: the input output is for interface, not for input loss. "

From the equipment”. Input-output devices require interfaces to be attached to the bus

Because of the error。

Reference answer:

Facilitate the integration of sites with storage units

44. In the microprocessor system, all external equipment will need to be connected by () circuit to the system bus

Go on。

Reference answer:

Interface

45. In the system where the i/o interface is centrally located, the storage module and the i/o interface are distinct () by。

Reference answer:

Different command address code

46. In the system where the i/o interface is independently located, the storage module and the i/o interface are distinct。

Reference answer:

Different command operation code

The last instruction to interrupt service proceedings should normally be ()。

Reference answer:

Abort return command

48. Programs prepared by programmers are stored in () modules when running in the arm system。

Reference answer:

Memory module

49. Interrupting the shielding function is generally ()。

Reference answer:

Pause the treatment of some interrupted sources

50. Errors resulting from the inability of a numerical volume to change continuously during the conversion of analogies to numerical quantities

Called ()。

Reference answer:

Quantified error

The following does not enhance data access parallels and throughput ()。

Reference answer:

2d address translation code storage device

52. Sp values decrease and sp points to the last entry when all data are entered

The next memory unit for stack data, which is referred to as ()。

Reference answer:

Empty decline

53. Sets a microprocessor system with a width of 13bit, by by bytes of address, and if assigned with full code

When a 1kx4bit chip is used to form a storage system, the maximum number of scalable chips is () chips。

Reference answer:

54. Primary storage in microcomputers is typically constructed using () semiconductor processes。

Reference answer:

Dram

The best explanation for stacking is () below。

Reference answer:

A memory area organized on a “back-in-first-out” basis

56. Among the factors listed below, what is not relevant is the cache hit rate ()。

Reference answer:

Main access time

In multi-level storage structures, cache's main role is to address () problems。

Insufficiency of primary access speed

58. If the memory of 64k capacity needs to be expanded, the following options are complex to connect from bus loads and systems:

From a point of view, the best is ()。

Reference answer:

Use a 64kx1bit chip

59. A sram storage chip has a data line width of 32bit and an address line width of 24bit, and the chip

Is the storage capacity ()。

Reference answer:

64mb

60. The purpose of adding a capacitor to the lines connected to the source foot of the chip and bringing it closer to the chip

Yes, it is。

Reference answer:

Increase the speed of the chip

61. In the lower quadrilateral cross-storage, the address to be visited by the processor (decimal) is 3, 6, 9

12, 15, 18, 21, 24, 300, which theoretically compares the memory to the average of the monomer

Speed has increased () multiple times。

Reference answer:

The following () modules are not required to run the arm system。

External application interface

63. The following () description is given in the version of the arm directive set (system structure)。

Reference answer:

64. The compound circuits in the minimum arm system are primarily used to generate ()。

Reference answer:

It's a low-level signal。

65. The following statement is correct。

Reference answer:

The primary memory is made up of random reading and writing memory that is easily lost

66. The location of the processor in the arm system is most accurately described ()。

Reference answer:

Soc chip

The location of the gps controller is most accurately described ()。

Reference answer:

Armsoc chip

On the s3c2440 chip, if you're going to use g-group gpio's seven feet for output, you're right down there

Yes ()。

Reference answer:

Write to gpgcon repository

Among the storage units listed below, the information will be lost after the loss of electricity ()。

Reference answer:

Sram

In the case of serial communications, the most accurate description of the method of connecting the equipment to and from both parties is ()。

Reference answer:

One device's txd foot and the other's rxd foot and txd foot, respectively

The following interpretation of the phrase “addrequ0x45500” is incorrect。

Reference answer:

The equ pseudo-director defines a variable in the execution of a program with an opening value of 0x45500

Flash storage is a () storage。

Reference answer:

Random reading and writing

The linux system divides equipment into three basic types, each of which corresponds to different forms of driving

These three types of equipment do not include the following ()。

Reference answer:

Virtual equipment

74. In soc design, the following statement is wrong: ()。

Reference answer:

It's more complicated hardware circuits

75. As regards the microcode cpu and the random logic cpu, the correct formulation is ()。

Reference answer:

It's easier to create new cpu versions

The cache memory in the micromechanical is usually constructed in () basic storage units。

Reference answer:

Sram

77. The main purpose of the tiered structure of the computer storage subsystems is ()。

Reference answer:

Facilitate resolution of conflicts between storage capacity, speed and price

78. The storage subsystems of modern computers typically include primary storage, cache, internal cpu repository, hard drives, etc

In part, they are (in descending order) according to the speed of access。

Reference answer:

Cpu internal repository, cache, master memory, hard disk

Instructions being implemented by computers should be stored within the cpu。

Command repository

The description of the special function register in arm is correct。

Reference answer:

Make address map addresses

81. In the following statement concerning the timing of the bus, the error is ()。

Reference answer:

Synchronized communication mode, synchronized clocks provided by equipment

82. With regard to serial communications, the correct statement is ()。

Reference answer:

There is no need for modem technology

83. In the bus system using the chrysanthemum chain arbitration programme, the following description of bus priorities is positive

Indeed ()

Reference answer:

The more you approach the front end of the chain, the higher the equipment priority

84. In general, synchronous serial communications are more efficient than the actual transmission of staggered communications because of synchronization

Serial communication ()。

Reference answer:

The protocol cost less and the additional data less

85. Port rate factor 64 in serial interface circuits, with receiving end(s) every () time the starting point is determined

The clock cycle receives a data bit。

Reference answer:

64

86. The main line connecting microprocessor chips, inner memory and i/o interface chips is ()。

Reference answer:

System bus

87. The 64-bit front-end bus frequency of a cpu is 800 mhz, the number of bus cycles is 2 and the bandwidth is

I'm sorry。

Reference answer:

3. 2gb/s

With regard to serial communications, the correct statement is ()。

Reference answer:

It's not necessarily a modem technique

89. In the common bus standard below, it is () that is a heterostring bus。

Reference answer:

Uart

90. A porter rate factor of 64 in the walk-through interface, with the receiver continuing over () sampling cycles

The starting point is not determined until the low level of electricity is received。

Reference answer:

32

91. For the bus standard below, which belongs to parallel bus(s)。

Reference answer:

Pci

92. The front end frequency of a cpu is 100 mhz, the number of bus cycles is 1/4 and the width 64bits

The bandwidth of the bus is () mb/s。

Reference answer:

3,200

Rs-232c data transmission is in () mode。

Reference answer:

Full and double

94. The following option () is a line bus。

Reference answer:

Sata

95. System data access width means ()。

Reference answer:

Data bits that can be transmitted in parallel

In the description of the bus below, the error is ()。

Reference answer:

Pci bus does not support break-up group transport

97. In synchronized parallel communication systems, usually a bus cycle is always ()。

Reference answer:

Send the address, then the data

98. Set the porter rate factor at 32 and the character length at 8 bits (including 1 bit of odd) during the work on the walk-through mode

Checkpoint) 1-bit, stop 2-bit, transfer 200 characters per second, then pass it

The rate of transmission and the frequency of incoming/offer clocks are respectively ()。

Reference answer:

2200bps, 70. 4khz

99. If the following character code has a quiz, but there is no data error, then an occasional character is used code

Yes ()。

Reference answer:

The rs-232c standard provides for a difference in voltage of more than 6v between logic “0” and “1”, the main significance of which is that

I'm sorry。

Reference answer:

It enhances the ability to resist interference

101. In amba bus, the apb bridge is ()。

Reference answer:

Only bus host in apb

102. In accordance with the principle of bus sharing, () more than one device in order to avoid confusion in signal logic and damage to the device

Output leads to share a signal line。

Reference answer:

Allows output pointers when they have a three-state function

103. The width of the microprocessor address bus is 32 bit, the width of its internal data bus ()。

Reference answer:

There's no automatic connection to the address bus

104. In the third bus structure of the computer system, for the transmission of reading/letter numbers is ()。

Reference answer:

Control bus

When the keyboard interface connects to the amba bus in the plate, it should be connected to the () bus。

Reference answer:

Apb

106. For the bus standard below, which does not belong to a single bus ()。

Reference answer:

Pci

107. The clock cycle of a non-flowing machine is 10ns. Alu and branch instructions for testing procedures are required

For 4 clock cycles, storage operational instructions require 5 clock cycles, 40% of the above

20% and 40%. Upgrade it to a 4-grade flow line. Clock cycle. Change

For 11ns, the acceleration ratio equals ()。

Reference answer:

4. 0

For the following indicators, the width of the cpu data is not directly linked ()。

Reference answer:

Command number

In the following arm directive, there was no error(s)。

Reference answer:

Ldmfdsp

With respect to the description of risc and cisc, the error is () below。

Reference answer:

The average rissc commands more than cisc

The cpu internal operator consists of several small components, the core of which is ()。

Reference answer:

Mathematical logic module

112. The main advantage of the use of interruptive controls compared with the mode of searching when the mainframe exchanges data with an external location is that

I'm sorry。

Reference answer:

The system is more real-time

113. Synchronization and harmonization of data formats between hosts and off-site data exchange

Questions like this have to be introduced。

Reference answer:

I/o interface

The following means of data transmission that do not require cpu to execute the directive are ()。