1 in the second semester of the school year 2013-2014, the computer composition principle i intermediate examination volume specializing in: information management level: general higher education grade: school number 2012 name: i, explaining the following concepts: 1: storage unit: 2; storage length: 3; storage capacity: 4; machine length: 5, pc: 6, mar: 7, mdr: 8, mips: 9; synchronized communication: 10: storage bandwidth: 2; 8 microcard addresses are 18; if using 4kx4-bit storage of the structure of the module, test: (1) what is the maximum primary storage space allowed by the machine? (2) how many modules do you need if each panel is 32kx 8? (3) how many ra chips are there in each modular plate? (4) how many ram(5) cpis are selected? Solve: (1) maximum master space allowed by the machine is 218 x 8
2 bit = 256 kx 8 bit = 256 kb (2) total number of modules = 256 kx 8 / 32 k x 8 = 8 block (3) number of plates = 32 kx8 bit / 4 k x4 bit = 8 x 2 = 16 piece (4) total number of pieces = 16 x 8 = 128 piece (5) cpu selects the template by means of a top 3-bit translation, and the sub-high 3-bit translation output selects the chip. As follows: cache organization with a template number (3 bit) chip number (3 bit) with an inner address (12), with a master capacity of 4mb cache with a capacity of 16kb, with 8 words per word, 32 bits per word, and a four-route image (i. E., 4 blocks per group of cache) requires: (1) drawing the number of bits in each section of the primary address field; (2) setting cache's initial state to be empty
3, cpu read 100 words (one word at a time) sequentially from the primary archive nos. 0, 1, 299 and read eight times in this order. What was the hit rate? (3) if cache is six times as fast as the main stock, how much faster is it compared to cache without cache? (1) as the capacity is byte, the primary address field format is as follows: the primary block tag group address in the block address group has a 3-byte address in the 872 word block address(2) because the word address given in the title is continuous, the minimum of two places in the address format in (1) do not participate in the word reading operation. When the primary type 0 is used, the primary number 0 (07) is transferred to cache (group 0 x block), while the primary number 8 is used, the first block (815) is moved to cache (group 1 x block) to the primary number 96 unit, and the 12th is used when the primary number 96 unit is used
4 block (96103) to cache (12 group x block). A total of 100/813 transfers are required to transfer 100 of the main stock to cache. The cpu is required to access the master memory 13 times during the first reading, and no access to the master memory is required for subsequent repeat reading. In 800 reading operations: the number of visits to cache = (100-13) + 700 = 787: -0. 98: - cache = 787/80098 (3) 800 t (t for primary storage) for access to cache when there is no cache, 800 t/(787*t/6) + 13*t) = 5. 55 times cache and no cache, which is about 4. 55 times faster. Iv. The disk group has six disks, each with two documentaries, with a 22 cm radius within the storage area, and outside
5 33 cm diameter, 40 cm tunnel density, 400 cm inner layer density, 2400 cm rotation, asking: (i) how many storage surfaces are available? (2) how many pillars are there? (3) what is the total stock storage capacity? (4) what is the data transmission rate? (i) if two layers of protection are removed, there will be a total of 6 x2 - 2 = 10 storage surfaces available; (ii) effective storage area = (33 - 22) / 2 = 5. 5 cm x 5. 5 = 220 cm (3) inner length = 22*3. 14 = 69. 08 cm = 400 b/cm x 69. 08 cm = 3454 b = 3454 b x 220 = 759,880 b-group total capacity = 759,880 b = 759,880 b x 10 side = 7,598,800 b
6, (4) turn = 2,400 turns/60 seconds = 40 turns/s data transmission rate = 3454b x 40 turns/s = 138, 160 b/s,: i 7. Note: 1) the volume of the disc should generally be calculated by removing the upper and lower protection surfaces; (2) the accuracy of the selection will give rise to different answers, usually taking two decimals; (3) the total number of disk channels = the number of columns (= magnetic channels on a plate)4 is not related to the number of panels; (5) the data transmission rate is in seconds, not fractions. Solving: effective information is n = 4 bits, assuming valid information is b1b2b3b4 = k = 3 bits, 2c2b1c4b2b3b4 = c1, c2 and c4 = 7 bits, i. E.:
7c1 c1 c1 1 c1 1 1 1 c1 = 1 1 c1 1 = 1 c1 1 = 1 1 = 1 c1 = 1 = 10 1 = 0 = 0 0 = 0 = 0 when valid information is 1101, hming code 101006, cp 16 address lines, 8 data lines, and mreq (low level effective) for access storage, r/w for reading and writing command signals (high level read and low level written). 8 existing 8k8-bit racs are linked to cpu, with an answer: (1) draw a cpu connection to the memory chip with 74138 coders; (2) write an address range for each ram; and (1) cpu connects to the memory chip logical map: +5v(2) address spatial distribution map: ram0:000h-1ffhram1:2000h-3ffhram2:4000h-5ff
8. Fhram3:6000 h-7ffhram4:8000 h-9ffh ram5:a000h-bffhram6:c000h-dffh ram7:e000h - [y]h(3) if, when running, it is found that the storage chip (ram5) with the aooh as its initial address has the same data, the underlying cause of the failure is that the selected input end of the memory chip is likely to always be low-level. Assuming that both the chip and the transcoder are themselves good, the possible scenarios are: 1) the --cs end of the film is wrong or short-circuited; 2) the --cs end of the film is wrong or short-circuited with the --mreq end of the cpu; 3) the --cs end of the film is wrong or short-circuited. (4) if the address line a13 is cut off from cpui and connected to the high level of electricity, the situation will remain consistent with a13 as “1”. At this point, the memory can only find the address space of a13 = 1 (odd pieces), and the other half of the address space of a13 = 0 (even pieces) will never be accessible. Access to a13 = 0 address space (even pieces) can only be obtained by error to the corresponding a13 = 1 space (odd pieces)。
